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ca16-type 2.5 gbits/s dwdm transponder with 16-channel 155 mbits/s multiplexer/demultiplexer advance data sheet march 2001 the ca16-type transponders integrate up to 15 discrete ics and optical components, i ncluding a 2.5gbits/s op- tical transmitter and receiver pair, all in a single, com- pact package. features 2.5 gbits/s optical transmitter and receiver with 16-channel 155 mbits/s multiplexer/demultiplexer. available with 1.55 m cooled dfb laser transmit- ter and an apd receiver for long-reach applica- tions: ? offers 45 standard itu wavelengths with 100 ghz spacing. ? each module is capable of two wavelengths under user control. pigtailed, low-profile package. differential lvpecl data interface. operating case temperature range: 0 c to 65 c. automatic transmitter optical power control. laser bias monitor output. transmitter laser disable input. line loopback and diagnostic loo pback capab ilit y . multiple alarms: ? loss of signal. ? loss of reference clock. ? loss of framing. ? laser degrade alarm. applications telecommunications: ? inter- and intraoffice sonet/sdh ? subscriber loop ? metropolitan area networks high-speed data communications description the ca16-type transponder performs the parallel-to- serial-to-optical transport and optical transport-to- serial-to-parallel function of the section and photonic layers of the sonet/sdh protocol. the ca16 trans- mitter section performs the bit serialization and opti- cal transmission of sonet/sdh oc-48/stm-16 data that has been formatted into standard sonet/ sdh compliant 16-bit parallel format. the ca16 receiver performs the optical-to-electrical conversion function and is then able to detect frame and byte boundaries and demultiplex the serial data into 16-bit parallel oc-48/stm-16 format. the ca16 transponder does not perform byte-level multiplexing or interleaving.
2 table of contents agere systems inc.. contents page tables page ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 features ................................................................... 1 applications .............................................................. 1 description ............................................................... 1 absolute maximum ratings ...................................... 3 block diagram........................................................... 4 pin information ......................................................... 5 pin descriptions ....................................................... 6 functional description ........................................... 12 receiver ............................................................ 12 transmitter ........................................................ 12 loopback modes ............................................... 13 transponder interfacing ..................................... 13 optical characteristics ........................................... 15 electrical characteristics ........................................ 16 timing characteristics ........................................... 18 transmitter data input timing ........................... 18 input timing mode 1 .......................................... 19 input timing mode 2 .......................................... 20 forward clocking ............................................... 21 pc lk -to pic lk timing ........................................ 22 pherr/phinit .................................................. 23 receiver framing ............................................... 25 wavelength selection ............................................. 26 qualification and reliability .................................... 27 laser safety information ....................................... 27 class i laser product ......................................... 27 electromagnetic emissions and immunity.......... 27 outline diagram ..................................................... 28 ordering information .............................................. 29 related product information ................................... 29 table 1. ca16-type transponder pin out ................. 6 table 2. ca16-type transponder input pin descriptions ...............................................10 table 3. ca16-type transponder output pin descriptions ...............................................11 table 4. oc-48/stm-16 transmitter optical characteristics ..........................................15 table 5. oc-48/stm-16 receiver optical characteristics ..........................................15 table 6. power supply characteristics .................... 16 table 7. transmitter electrical i/o characteristics... 16 table 8. receiver electrical i/o characteristics ...... 17 table 9. transmitter ac timing characteristics ....... 24 table 10. receiver ac timing characteristics ......... 24 table 11. ordering information ................................ 29 table 12. related product information .................... 29 figures page figure 1. ca16-type transponder block diagram....4 figure 2. ca16-type transponder pinout ................. 5 figure 3. transponder interfacing............................ 13 figure 4. interfacing to the t x r ef c lk input............. 14 figure 5. block diagram timing mode 1.................. 19 figure 6. block diagram timing mode 2.................. 20 figure 7. forward clocking of the ca16 transponder .................................. 21 figure 8. pc lk -to pic lk timing...............................22 figure 9. pherr/phinit timing.............................23 figure 10. ac input timing ....................................... 24 figure 11. receiver output timing diagram ........... 24 figure 12. frame and byte detection ......................25 figure 13. oof timing (framen = high) ..............25 figure 14. framen timing.....................................26
3 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer description (continued) figure 1 shows a simplified block diagram of the ca16- type transponder. this device is a bidirecti onal m odule designed to provide a sonet or sdh compliant elec- tro-optical interface between the sonet/sdh photonic physical layer and the electrical section layer. the mod- ule contains a wavelength-tunable (two channels at 100 ghz) 2.5 gbits/s optical transmitter and a 2.5 gbits/s optical receiver in the same physical pack- age along w ith the electronics nece ssary to multiplex and demultiplex sixteen 155 mbits/s electrical channels. clock synthesis, clock recovery, and sonet/sdh frame detection circuits are also included within the module. in the transmit direction, the trans ponder m odule m ulti- plexes sixteen 155 mbits/s pecl electrical data signals into an optical signal at 2488 .32 mbit s/s for l aunching into optical fiber. an internal 2.488 ghz reference oscil- lator is phase-locked to an external 155.52 mhz data timing reference. the optical transmitter is available at any itu grid wavelength with a 1.55 m cooled dfb laser for long- reach applications. the optical output signal is sonet and itu compliant for oc-48/stm-16 applications as shown in table 4, oc-48/stm-16 transmitter optical characteristics. in the receive direction, the transponder module receives a 2488.32 mbits/s optical signal and converts it to an electrical signal, and then extracts a clock sig- nal and demultiplexes the data into sixteen 155 mbits/s differential lvpecl data signals. when enabled, the module can also detect sonet/sdh frame bound- aries. the optical receiver is available with an apd photodetector. the receiver operates over the wave- length range of 1.1 m to 1.6 m and is fully compliant to sonet/sdh oc-48/stm-16 physical layer specifi- cations as shown in table 5, oc-48/stm-16 receiver optical characteristics. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. exposure to absolute maximum ratings for ex tended periods can adversely affect reliability. 1. human body model. parameter symbol min max unit operating case temperature range t c 075c storage case temperature range t s ?40 85 c supply voltage ? ?0.5 5.5 v voltage on any lvpecl pin ? 0 v cc ? high-speed lvpecl output source current ? ? 50 ma static discharge voltage 1 esd ? 500 v relative humidity (noncondensing) rh ? 85 % receiver optical input power?biased apd p in ?0dbm minimum fiber bend radius ? 1.25 (31.8) ? in. (mm)
4 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 block diagram figure 1. ca16-type transponder block diagram oc-48/stm-16 optical transmitter d ck d oc-48/stm-16 optical receiver w/clock recovery 16:1 parallel timing clock divider frame/byte timing 1:16 serial mux mux txdis mux generation to serial and phase detect detect gen to parallel mux wdea lsr alrm lpm txd[0:15]p txd[0:15]n piclkp/n phinit pherr pclkp/n txrefclkp/n lloop dloop oof search fp poclkp/n rxq[0:15]p rxq[0:15]n los 16 16 2 2 2 2 16 16 framen ws (wavelength select) lockdet reset ipdmon 1-1011(f).f
5 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer pin information 1-1014(f).d figure 2. ca16-type transponder pinout rxq13n rxq13p rxq15n rxq15p rxdgnd vtec vtec ws nc poclkn poclkp rx3.3a rxagnd rxagnd search rx3.3d rx3.3d rxdgnd oof rxdgnd los lloop pherr nc txdis phinit nc tx3.3a tx3.3d txagnd txdgnd pclkn pclkp txdgnd txd00n txd00p txdgnd txd02n txd02p txd04n txd04p txdgnd txd06n txd06p txd08n txd08p txdgnd txd10n txd10p txd12n txd12p txdgnd txd14n txd14p txrefclkn txdgnd reset fgnd rxdgnd rxq12n rxq12p rxq14n rxq14p rxdgnd vtec vtec vtec rxdgnd rxagnd rxagnd rx3.3a rxagnd rxagnd nc rx3.3d fp wdea dloop nc lsrbias lsralm lpm txagnd tx3.3a tx3.3a txagnd tx3.3d tx3.3d txdgnd lockdet piclkn piclkp txdgnd txd01n txd01p txd03n txd03p txdgnd txd05n txd05p txd07p txdgnd txd09n txd09p txd11n txd11p txdgnd txd13n txd13p txd15n txd15p txdgnd ipdmon fgnd rxdgnd 140 60 130 50 120 40 110 30 100 20 90 10 1 81 tx txrefclkp txd07n framen rx3.3d rxdgnd rxq05n rxq05p rxq07n rxq07p rxdgnd rxq09n rxq09p rxq11n rxq11p rxdgnd rxq04n rxq04p rxq06n rxq06p rxdgnd rxq08n rxq08p rxq10n rxq10p rxdgnd 150 70 nc nc nc nc rxdgnd rxq01n rxq01p rxq03n rxq03p fgnd nc nc nc nc rxdgnd rxq00n rxq00p rxq02n rxq02p fgnd 160 80 rx top view
6 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 pin descriptions table 1. ca16-type transponder pinout pin # pin name i/o logic description 01 fgnd i supply frame ground 1 02 ipdmon o analog receiver photodiode current monitor 03 txdgnd i supply transmitter digital ground 04 txd15p i lvpecl transmitter 155 mbits/s msb data input 05 txd15n i lvpecl transmitter 155 mbits/s msb data input 06 txd13p i lvpecl transmitter 155 mbits/s data input 07 txd13n i lvpecl transmitter 155 mbits/s data input 08 txdgnd i supply transmitter digital ground 09 txd11p i lvpecl transmitter 155 mbits/s data input 10 txd11n i lvpecl transmitter 155 mbits/s data input 11 txd09p i lvpecl transmitter 155 mbits/s data input 12 txd09n i lvpecl transmitter 155 mbits/s data input 13 txdgnd i supply transmitter digital ground 14 txd07p i lvpecl transmitter 155 mbits/s data input 15 txd07n i lvpecl transmitter 155 mbits/s data input 16 txd05p i lvpecl transmitter 155 mbits/s data input 17 txd05n i lvpecl transmitter 155 mbits/s data input 18 txdgnd i supply transmitter digital ground 19 txd03p i lvpecl transmitter 155 mbits/s data input 20 txd03n i lvpecl transmitter 155 mbits/s data input 21 txd01p i lvpecl transmitter 155 mbits/s data input 22 txd01n i lvpecl transmitter 155 mbits/s data input 23 txdgnd i supply transmitter digital ground 24 pic lk p i lvpecl byte-aligned parallel input clock at 155 mhz 25 pic lk n i lvpecl byte-aligned parallel input clock at 155 mhz 26 lockdet o lvttl lock detect 27 txdgnd i supply transmitter digital ground 28 tx3.3d i supply transmitter 3.3 v digital supply 29 tx3.3d i supply transmitter 3.3 v digital supply 30 txagnd i supply transmitter analog ground 31 tx3.3a i supply transmitter 3.3 v analog supply 32 tx3.3a i supply transmitter 3.3 v analog supply 33 txagnd i supply transmitter analog ground 34 lpm o analog laser power monitor 35 lsralm o 5 v cmos laser degrade alarm 36 lsrbias o analog not implemented on the ca16-type transponder 37 nc ? ? no user connection permitted 2 38 d loop i lvttl diagnostic loopback 39 wdea o 5 v cmos wavelength deviation error alarm 40 fp o lvpecl frame pulse 41 framen i lvttl frame enable 1. frame ground is connected to the housing and is i solated from all circuit gr ounds (t xdgnd, txagnd, rxdgnd, rxagnd). 2. pins labeled no connection must remain open circuits; they have inter nal volt ages and must not be connected to v cc , ground, or any signal node.
7 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer 42 rxdgnd i supply receiver digital ground 43 rx3.3d i supply receiver 3.3 v digital supply 44 rx3.3d i supply receiver 3.3 v digital supply 45 nc ? ? no user connection permitted 2 46 rxagnd i supply receiver analog ground 47 rxagnd i supply receiver analog ground 48 rx3.3a i supply receiver 3.3 v analog supply 49 rxagnd i supply receiver analog ground 50 rxagnd i supply receiver analog ground 51 rxdgnd i supply receiver digital ground 52 vtec i supply tec cooler 3 v analog s upply voltage 53 vtec i supply tec cooler 3 v analog s upply voltage 54 vtec i supply tec cooler 3 v analog s upply voltage 55 rxdgnd i supply receiver digital ground 56 rxq14p o lvpecl receiver 155 mbits/s data output 57 rxq14n o lvpecl receiver 155 mbits/s data output 58 rxq12p o lvpecl receiver 155 mbits/s data output 59 rxq12n o lvpecl receiver 155 mbits/s data output 60 rxdgnd i supply receiver digital ground 61 rxq10p o lvpecl receiver 155 mbits/s data output 62 rxq10n o lvpecl receiver 155 mbits/s data output 63 rxq08p o lvpecl receiver 155 mbits/s data output 64 rxq08n o lvpecl receiver 155 mbits/s data output 65 rxdgnd i supply receiver digital ground 66 rxq06p o lvpecl receiver 155 mbits/s data output 67 rxq06n o lvpecl receiver 155 mbits/s data output 68 rxq04p o lvpecl receiver 155 mbits/s data output 69 rxq04n o lvpecl receiver 155 mbits/s data output 70 rxdgnd i supply receiver digital ground 71 rxq02p o lvpecl receiver 155 mbits/s data output 72 rxq02n o lvpecl receiver 155 mbits/s data output 73 rxq00p o lvpecl receiver 155 mbits/s lsb data output 74 rxq00n o lvpecl receiver 155 mbits/s lsb data output 75 rxdgnd i supply receiver digital ground 76 nc ? ? no user connection permitted 2 77 nc ? ? no user connection permitted 2 78 nc ? ? no user connection permitted 2 79 nc ? ? no user connection permitted 2 80 fgnd i supply frame ground 1 81 fgnd i supply frame ground 1 82 reset i ? master reset pin # pin name i/o logic description pin descriptions (continued) table 1. ca16-type transponder pinout (continued) 1. frame ground is connected to the housing and is isolated from all circuit grounds (t xdgnd, txagnd, rxdgnd, rxagnd). 2. pins labeled no connection must remain open circuits; they have internal voltages and must not be con nected to v cc , ground, or any signal node.
8 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 83 txdgnd i supply transmitter digital ground 84 txr ef c lk p i lvpecl transmitter 155 mbits/s reference clock input 85 txr ef c lk n i lvpecl transmitter 155 mbits/s reference clock input 86 txd14p i lvpecl transmitter 155 mbits/s data input 87 txd14n i lvpecl transmitter 155 mbits/s data input 88 txdgnd i supply transmitter digital ground 89 txd12p i lvpecl transmitter 155 mbits/s data input 90 txd12n i lvpecl transmitter 155 mbits/s data input 91 txd10p i lvpecl transmitter 155 mbits/s data input 92 txd10n i lvpecl transmitter 155 mbits/s data input 93 txdgnd i supply transmitter digital ground 94 txd08p i lvpecl transmitter 155 mbits/s data input 95 txd08n i lvpecl transmitter 155 mbits/s data input 96 txd06p i lvpecl transmitter 155 mbits/s data input 97 txd06n i lvpecl transmitter 155 mbits/s data input 98 txdgnd i supply transmitter digital ground 99 txd04p i lvpecl transmitter 155 mbits/s data input 100 txd04n i lvpecl transmitter 155 mbits/s data input 101 txd02p i lvpecl transmitter 155 mbits/s data input 102 txd02n i lvpecl transmitter 155 mbits/s data input 103 txdgnd i supply transmitter digital ground 104 txd00p i lvpecl transmitter 155 mbits/s lsb data input 105 txd00n i lvpecl transmitter 155 mbits/s lsb data input 106 txdgnd i supply transmitter digital ground 107 pc lk p o lvpecl transmitter parallel reference clock output 108 pc lk n i lvpecl transmitter parallel reference clock output 109 txdgnd i supply transmitter digital ground 110 txagnd i supply transmitter analog ground 111 tx3.3d i supply transmitter digital 3.3 v supply 112 tx3.3a i supply transmitter analog 3.3 v supply 113 nc ? ? future function (i 2 c clock) 114 phinit i lvpecl phase initialization 115 t x dis i ttl transmitter disable 116 nc ? ? future function (i 2 c data) 117 pherr o lvpecl phase error 118 l loop i lvttl line loopback (active-low) 119 los o lvttl loss of signal 120 rxdgnd i supply receiver digital ground 121 oof i lvttl out of frame (enable frame detection) 122 rxdgnd i supply receiver digital ground 123 rx3.3d i supply receiver digital 3.3 v supply pin # pin name i/o logic description pin descriptions (continued) table 1. ca16-type transponder pinout (continued) 1. frame ground is connected to the housing and is i solated from all circuit gr ounds (t xdgnd, txagnd, rxdgnd, rxagnd). 2. pins labeled no connection must remain open circuits; they have inter nal volt ages and must not be connected to v cc , ground, or any signal node.
9 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer 1. frame ground is connected to the housing and is i solated from all circuit gr ounds (t xdgnd, txagnd, rxdgnd, rxagnd). 2. pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to v cc , ground, or any signal node. 124 rx3.3d i supply receiver digital 3.3 v supply 125 search o lvttl frame search output 126 rxagnd i supply receiver analog ground 127 rxagnd i supply receiver analog ground 128 rx3.3a i supply receiver analog 3.3 v supply 129 poc lk p o lvpecl byte-aligned parallel output clock at 155 mhz 130 poc lk n o lvpecl byte-aligned parallel output clock at 155 mhz 131 nc ? ? no user connection permitted 2 132 ws i lvttl binary input to select one of two grid wavelengths 133 vtec i supply tec cooler 3 v analog supply voltage 134 vtec i supply tec cooler 3 v analog supply voltage 135 rxdgnd i supply receiver digital ground 136 rxq15p o lvpecl receiver msb 155 mbits/s data output 137 rxq15n o lvpecl receiver msb 155 mbits/s data output 138 rxq13p o lvpecl receiver 155 mbits/s data output 139 rxq13n o lvpecl receiver 155 mbits/s data output 140 rxdgnd i supply receiver digital ground 141 rxq11p o lvpecl receiver 155 mbits/s data output 142 rxq11n o lvpecl receiver 155 mbits/s data output 143 rxq09p o lvpecl receiver 155 mbits/s data output 144 rxq09n o lvpecl receiver 155 mbits/s data output 145 rxdgnd i supply receiver digital ground 146 rxq07p o lvpecl receiver 155 mbits/s data output 147 rxq07n o lvpecl receiver 155 mbits/s data output 148 rxq05p o lvpecl receiver 155 mbits/s data output 149 rxq05n o lvpecl receiver 155 mbits/s data output 150 rxdgnd i supply receiver digital ground 151 rxq03p o lvpecl receiver 155 mbits/s data output 152 rxq03n o lvpecl receiver 155 mbits/s data output 153 rxq01p o lvpecl receiver 155 mbits/s data output 154 rxq01n o lvpecl receiver 155 mbits/s data output 155 rxdgnd i supply receiver digital ground 156 nc ? ? no user connection permitted 2 157 nc ? ? no user connection permitted 2 158 nc ? ? no user connection permitted 2 159 nc ? ? no user connection permitted 2 160 fgnd i supply frame ground 1 pin # pin name i/o logic description pin descriptions (continued) table 1. ca16-type transponder pinout (continued)
10 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 pin descriptions (continued) * future versions of the cooled transponder will not support the frame-detect function. table 2. ca16-type transponder input pin descriptions pin name pin description txd[0:15]p txd[0:15]n 16-bit differential lvpecl parallel input data bus . txd15p/n is the most significant bit of the input word and is the first bit serialized. txd00p/n is the least significant bit of the input word and is the last bit serialized. txd[0:15]p/n is sampled on the rising edge of pic lk . pic lk p pic lk n differential lvpecl parallel input clock . a 155 mhz nominally 50% duty cycle input clock to which txd[0:15]p/n is aligned. the rising edge of pic lk transfers the data on the 16 txd inputs into the holding register of the parallel-to-serial converter. txr ef c lk p txr ef c lk n differential lvpecl low jitter 155.520 mhz input reference clock . this input is used as the reference for the internal clock frequency synthesizer, which g enerates the 2.5 ghz bit rate clock used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which transfers the 16-bit parallel input data from the input holding register into the parallel-to-serial shift register. input is internally terminated and biased. see discussion on timing interface, page 18. txdis transmitter disable input . a logic high on this input pin shuts off the transmitter?s laser so that there is no optical output. ws wavelength select. when this input is a logic 0 or left float ing, the output wavelength will be the nominal wavelength (at 25 c); when it is a logic 1, the wavelength will increase by approximately 0.8 nm (100 ghz frequency decr ease). dloop diagnostic loopback enable (lvttl) . when the d loop input is low, the 2.5 gbits/s serial data stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel con- verter along with an internally generated bit synchronous serial clock. the received serial data path from the optical receiver is disabled. lloop line loopback enable (lvttl) . when l loop is low, the 2.5 gbits/s serial data and recovered clock from the optical receiver are lo oped directly back to the optical transmitter. the multiplexed serial data from the parallel-to-serial converter is ignored. phinit phase initialization (single-ended lvpecl) . this input is used to align the internal elastic store (fifo). a rising edge on phinit will realign the inter nal timing (see fifo d iscussion, pages 12 and 18). framen * frame enable input (lvttl) . enables the frame detection circuitry to detect a1, a2 byte align- ment and to lock to a word boundary. the ca16 transponder will con tinually perform frame acqui- sition as long as framen is held high. w hen this i nput is low, the frame-detection circuitry is disabled. frame-detection process is initiated by rising edge of out-of-frame pulse. oof * out of frame (lvttl) . this input indicator is typically generated by external sonet/sdh over- head monitor circuitry in response to a state in which the frame boundaries of the received sonet/sdh signal are unknown, i.e., after system reset or loss of synchronization. the rising edge of the oof input initiates the frame detection function if framen is high. the fp output goes high when the frame boundary is detected in the incoming serial data stream from the opti- cal receiver. reset master reset (lvttl). reset input for the multiplexer and demultiplexer. a logic low on this input clears all buffers and registers. during reset, poc lk and pc lk do not toggle.
11 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer pin descriptions (continued) * future versions of the cooled transponder will not support the frame-detect function. table 3. ca16-type transponder output pin descriptions pin name pin description rxq[0:15]p rxq[0:15]n 16-bit differential lvpecl parallel output data bus . rxq[0:15] is the 155 mbyte/s 16-bit output word. rxq15p/n is the most significant bit of the received word and is the first bit serialized. rxq00p/n is the least significant bit of the received word and is the last bit serialized. rxq[0:1 5]p/ n is updated on the falling edge of poc lk . poc lk p poc lk n differential lvpecl parallel output clock . a 155 mhz nominally 50% duty cycle, byte rate out- put clock that is aligned to the rxq[0:15] byte serial output data. rxq[0:15] and fp are updated on the falling edge of poc lk . fp * frame pulse (lvpecl). indicates frame boundaries in the received serial data stream. if framing pattern detection is enabled (framen high and oof), fp pul ses high for one poc lk cycle when a 32-bit sequence match ing the framing pattern is detected in the received serial data. fp is updated on the falling edge of poc lk . search * a1 a2 frame search output (lvttl) . a high on this output pin indicates that the frame detection circuit is active and is searching for a new a1 a2 byte alignment. this output will be high during the entire a1 a2 frame search. once a new alignment is found, this si gnal will rem ain high for a mini- mum of one 155 mhz clock period beyond the third a2 byte before it will be set low. los loss of signal (lvttl) . a low on this output indicates a loss of clock by the clock recovery circuit in the optical receiver. lsrbias laser bias alarm (analog) . the analog bias alarm is not available on the ca16 transpo nders. lsralm laser degrade alarm (5 v cmos). this output goes to a logic 0 when the laser output power degrades 2 db below the nomi nal output power. lpm laser power monitor (analog) . provides an indication of the output power level from the transmit- ter laser. this output is set at 500 mv for the nominal transmitter optical output power. if the optical power decreases by 3 db, this output will drop to approximately 250 mv, and if the output power should increase by 3 db, this output will increase to 1000 mv. pc lk p/n parallel byte clock (differential lvpecl) . a byte-rate reference clock generated by dividing the internal 2.488 ghz serial bit clock by 16. this output is normally used to synchronize byte-wide transfers from upstream logic into the ca16 transponder. see timing discussion for additional details, page 18. pherr phase error signal (single-ended lvpecl) . pulses high during each pc lk cycle for which there is a poten tial setup/hold timing violation between the internal byte clock and the pic lk timing domain. pherr is updated on the falling edge of the pc lk outputs. ipdmon receiver photodiode current monitor (analog). this output provides a current output that is a mirror of the of the photocur rent generated by the optical receiver?s photodetector diode (apd or pin). a 10 k ? resistor from pin 2 to ground prov ides a voltage at this output ranging from ~1 mv to ~800 mv, depending on the optical input power. wdea wavelength deviation alarm (5 v ttl). this output changes logic levels whenever the optical transmitter?s wavelength deviates from the nominal wavelength by more than 100 pm. lockdet lock detect (lvttl). this output goes low after the transmit side pll has locked to the clock sig- nal provided at the t x r ef c lk input pins. lockdet is an asychronous output.
12 12 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 functional description receiver the optical receiver in the ca16-type transponder has an apd and is optimized for the particular sdh/sonet application segment in which it was designed to operate. the detected serial data output of the optical receiver is connected to a clock and data recovery circuit (cdr), which extracts a 2488.32 mhz clock signal. this recov- ered serial bit clock signal and a retimed serial data signal are presented to the 16-bit serial-to-parallel converter and to the frame and byte detection logic. the serial-to-parallel converter consists of three 16-bit registers. the first is a serial-in parallel-out shift register, which performs serial-to-parallel conversion. the second is an internal 16-bit holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte detection logic. on the falling edge of the free-running poc lk signal, the data in the holding register is transferred to the output holding register where it becomes available as rxq[0:15]. note: future versions of the cooled trans ponder will not support the frame-detect function. the frame and byte boundary detection circuitry searches the incoming data for three consecutive a1 bytes followed immediately by an a2 byte. framing pattern detection is enabled and disabled by the framen i nput. the frame detection process is started by a rising edge on oof while framen is active (framen = high). it is disabled when a framing pattern is detected. when framing pattern detection is enabled (framen = high), the framing pat- tern is used to locate byte and frame boundaries in the incoming serial data stream from the cdr circuits. during this time, the parallel output data bus (rxq[0:15]) will not contain valid data. the timing generator circuitry takes the located byte boundary and uses it to block the incoming serial data stream into bytes for output on the parallel out- put data bus (rxq[0:15]). the frame boundary is reported on the framing pulse (fp) output w hen any 32-bit pattern matching the framing pattern is detected in the incoming serial data stream. when framing detection is disabled (framen = low), the byte boundary is fixed at the loca- tion found when frame detection was previously enabled. transmitter the optical transmitter in the ca16-type trans ponder is optimized for the particular sdh/sonet segment in which it is destined to operate. the transmitter has a cooled dfb laser as the optical element and operates at a nominal 1550 nm (45 standard itu wavelengths are avail- able for dwdm applications). under user control, the transmitter can switch to either one of two adjacent itu wavelengths (100 ghz spacing). the transmitter is driven by a serial data stream developed in the parallel-to-serial conversion logic and by a 2488.32 mhz serial bit clock sig- nal synthesized from the 155.52 mhz t x r ef c lk input. note that the clock divider and phase-detect circuitry shown in figure 1 generates internal reference clocks and timing functions for the transmitter. therefore, it is impor- tant that the txr ef c lk input is generated from a precise and stable source. to prevent internal timing signals from producing jitter in the transmitted serial data that exceeds the sdh/sonet jitter generation requirements of 0.01 ui, it is required that the txr ef c lk input be generated from a crystal oscillator or other source having a frequency accu- racy better than 20 ppm. in order to meet the sdh/ sonet jitter generation requirement, the reference clock jitter must be guaranteed to be less than 1 ps rms over the 12 khz to 20 mhz bandwidth. when used in sonet net- work applications, this input clock must be derived from a source that is synchronized to the primary reference clock. the timing generation circuitry provides two separate functions. it develops a byte rate clock that is synchro- nized to the 2488.32 mhz transmit serial clock, and it pro- vides a mechanism for aligning the phase between the incoming byte clock (pic lk ) and the clock that loads the parallel data from the input register into the parallel-to- serial shift register. the pc lk output is a byte rate (155 mhz) version of the serial transmit clock and is intended for use by upstream multiplexing and o verhead processing circuits. using pc lk for upstream circuits will ensure a stable frequency and phase relationship between the parallel data coming into the transmitter and the subsequent parallel-to-serial timing functions. in the parallel-to-serial conversion pro- cess, the incoming data is passed from the pic lk byte clock timing domain to the internally generated byte clock timing domain that is phase aligned to the internal serial transmit clock. the timing generator also produces a feed- back reference clock to the phase detector. a counter divides the synthesized clock down to the same frequency as the reference clock txr ef c lk . the parallel-to-serial converter shown in figure 1 is com- prised of an fifo and a parallel-to-serial register. the fifo input latches the data from the txd[0:15]p/n bus on the rising edge of pic lk . the parallel-to-serial register is a loadable shift register that takes parallel input from the fifo output. an internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock, as described above, activates the parallel data transfer between registers. the serial data is shifted out of the par- allel-to-serial register at the transmit serial clock rate.
13 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer functional description (continued) loopback modes the ca16-type transponder is capable of operating in either of two loopback modes: diagnostic loopback or line loopback. line loopback when l loop is pulled low, the rece ived ser ial data stream and recovered 2488.32 mhz serial clock from the optical receiver are connected directly to the serial data and clock inputs of the optical transmitter. this establishes a receive-to-transmit loopback at the serial line rate. diagnostic loopback when d loop is pulled low, a loopback path is estab- lished from the transmitter to the receiver. in this mode, the serial data from the parallel-to-serial converter and the transmit serial clock is looped back to the serial-to- parallel converter and the frame and byte detect cir- cuitry, respectively. transponder interfacing the txd[0:15]p/n, txr ef c lk p/n, and pic lk p/n inputs and the rxq[0:15]p/n, poc lk p/n, and pc lk p/ n outputs are high-speed (155 mbits/s), lvpecl differ- ential data and clock signals. to maintain optimum sig- nal fidelity, these inputs and outputs must be connected to their terminating devices via 50 ? con- trolled-impedance transmission lines. the transmitter inputs (txd[0:15]p/n, txr ef c lk p/n, and pic lk p/n) must be terminated as close as possible to the ca16 transponder connector with a thevenin equivalent impedance equal to 50 ? terminated to vcc ? 2 v. the receiver outputs (rxq[0:15]p/n, poc lk p/n, and pc lk p/n) must be terminated as close as possible to the device (ic) that these si gnals interface to with a thevenin equivalent im pedance equal to 50 ? termi- nated to vcc ? 2 v. figure 3, below, shows one e xample of the pr oper ter- minations. other methods may be used, provi ded they meet the requirements stated above. 1-1054(f) figure 3. transponder interfacing txd[0:15]p 130 ? 80 ? 80 ? 130 ? 3.3 v 130 ? 80 ? 80 ? 130 ? 3.3 v sonet/sdh rxline txline 50 ? impedance ca16-type transponder transmission lines 50 ? impedance transmission lines interface ic connector (lvpecl) txd[0:15]n (lvpecl) rxd[0:15]p (lvpecl) rxd[0:15]n (lvpecl) mux demux tx rx
14 14 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 functional description (continued) transponder interfacing (continued) txr ef c lk p/n the t x r ef c lk input is different than the other inputs to the transmitter because it is internally terminated, ac- coupled, and self-biased. therefore, it must be treated differently than the t x d and pic lk inputs. differentially, the input impedance at this i nput is 100 ? , but due to the way it is biased internally, when driven single- ended, the impedance appears as 60 ? . the proper termination scheme for the t x r ef c lk input is shown in figure 4. figure 4. interfacing to the txrefclk input interface ic (v cc = 3.3 v) pll clock synthesizer multiplexer ca16 transponder txrefclkp txrefclkn 50 ? transmission lines differential interface connector 100 ? 330 ? 330 ? sonet/sdh interface ic (v cc = 3.3 v) pll clock synthesizer multiplexer ca16 transponder txrefclkp txrefclkn 50 ? transmission lines single-ended interface connector 60 ? 330 ? 0.1 f 300 ? for a single-ended input, the input impedance is equivalent to 60 ?. sonet/sdh lvpecl lvpecl 1-1084 (f).c
15 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer optical characteristics minimum and maximum values spe cified over operating case temperature range at 50% duty cycle data signal. typical values are measured at room tempera ture unless otherwise noted. table 4. oc-48/stm-16 transmitter optical characteristics (tc = 0 c to 65 c) 1. output power definitions and measurements per itu-t recommendation g.957. 2. full spectral width measured 20 db down from the central wavelength peak under fully modula ted conditions. 3. ratio of the average output power in the domin ant longitudinal mode to the power in the most significant side mode under full y modulated conditions. 4. ratio of logic 1 output power to logic 0 output power under fully modulated conditions. 5. gr-253-core, synchronous optical network (sonet) transport systems: common generic criteria. 6. itu-t recommendation g.957, optical interfaces for equipment and systems relating to the synchronous digital hierarchy. table 5. oc-48/stm-16 receiver optical characteristics (tc = 0 c to 65 c) 1. at 1310 nm, 1 x 10 ?10 ber, 2 23 ? 1 pseudorandom data input. parameter symbol min typ max unit average output power: 1 long reach (1.55 m dfb laser) p o ?2 0 3 dbm operating wavelength: long reach (1.55 m dfb laser); all 48 100 ghz itu grid channels available 1528 ? 1563 nm variation in center wavelength over operating temperature (eol) ? ?0.06 ? 0.06 nm spectral width: long reach (dfb laser) 2 ? 20 ?? 1nm side-mode suppression ratio (dfb laser) 3 ssr 30 ? ? db extinction ratio 4 r e 8.2 ? ? db optical rise and fall time: ca16a2-type ca16b2-type t r , t f ? ? ? ? 140 130 ps ps dispersion penalty: ca16a2-type ca16b2-type dp ? ? ? ? 2.0 2.0 db db eye mask of optical output 5, 6 compliant with gr-253 and itu-t g.957 jitter generation compliant with gr-253 and itu-t g.958 parameter symbol min typ max unit average receiver sensitivity 1 : apd receiver p rmin ?29 ?34 ? dbm maximum optical power: apd receiver (long reach) p rmax ?8 ?6 ? dbm link status switching threshold: apd decreasing light input lstd ? tbd ? dbm link status response time ? 3 ? 100 s optical path penalty ? ? ? 2 db receiver reflectance ? ? ? ?27 db jitter tolerance and jitter transfer compliant with gr-253 and itu-t g.958
16 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 electrical characteristics table 6. power supply characteristics (tc = 0 c to 65 c) table 7. transmitter electrical i/o characteristics (t c = 0 c to 65 c, v cc = 3.3 v 5%) 1. 20% to 80%. 2. internally biased and ac-coupled. 3. the transmitter is normally enabled and only requires an external vol tage to disable. 4. the wdea alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm. 5. set at 500 mv at nominal optical output power. provides linear p o tracking (?3 db = 250 mv, +3 db = 1000 v). 6. terminated into 200 ? to gnd and 100 ? line-to-line. parameter symbol min typ max unit supply voltage v cc 3.13 3.3 3.47 v dc power supply current drain i cc ? 2000 ? ma tec voltage v tec 3.0 3.3 3.5 v tec-only current drain tec_i cc ? 0.6 1200 ma power dissipation p diss ?<9 ?w parameter symbol logic min typ max unit parallel input clock pic lk p/n diff. lvpecl 153.90 155.52 157.00 mhz parallel clock in duty cycle ? ? 40 ? 60 % reference clock freq. tolerance txr ef c lk p/n diff. lvpecl ?20 ? 20 ppm reference clock input duty c ycle ? ? 30 ? 70 % reference clock rise and fall time 1 t r , t f ???0.5ns reference clock signal levels 2 : differential input signal level, ? v indiff single-ended input sig. level, ? v insingle differential input resistance, ? r txr ef c lk diff. lvpecl 300 150 80 ? ? 100 1200 600 120 mv mv ? input data signal levels: input high, v ih input low, v il input voltage swing, ? v in txd[0:15]p/n diff. lvpecl v cc ? 1.2 v cc ? 2.0 300 ? ? ? v cc ? 0.3 v cc ? 1.5 ? v v mv transmitter disable input 3 txd is ttl (5 v) 2.0 ? 5.0 v transmitter enable input 3 txe n ttl (5 v) 0 ? 0.8 v wavelength-select voltage: channel n select, v n channel n ? 1 select, v n?1 ws ttl 0 2.0 ? ? 0.8 v cc v v wavelength deviation alarm: normal mode, v no-alarm wavelength alarm, v alarm alarm setting (active-high) 4 wdea ttl 0 4.5 ?100 ? ? ? 0.3 5 100 v v pm laser degrade alarm: normal mode, v no-alarm laser degraded, v alarm lsralm ttl 4.5 0 ? ? 5 0.3 v v laser power monitor output 5 lpm analog 35 500 1000 mv phase initialization: input high, v ih input low, v il phinit lvpecl v cc ? 1.0 v cc ? 2.3 ? ? v cc ? 0.57 v cc ? 1.44 v v
17 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer electrical characteristics (continued) 1. 20% to 80%. 2. internally biased and ac-coupled. 3. the transmitter is normally enabled and only requires an exter nal voltage to disable. 4. the wdea alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm. 5. set at 500 mv at nominal optical output power. provides linear p o tracking (?3 db = 250 mv, +3 db = 1000 v). 6. terminated into 200 ? to gnd and 100 ? line-to-line. table 8. receiver electrical i/o characteristics (tc = 0 c to 65 c, vcc = 3.3 v 5%) 1. terminated into 330 ? to ground. 2. 20% to 80%, 330 ? to ground. table 7. transmitter electrical i/o characteristics (t c = 0 c to 65 c, v cc = 3.3 v 5%) (continued) parameter symbol logic min typ max unit phase error 5 : output high, v oh output low, v ol pherr lvpecl v cc ? 1.2 v cc ? 2.2 ? ? v cc ? 0.65 v cc ? 1.5 v v line loopback enable: active-low: input high, v ih input low, v il l loop lv t t l 2.0 0 ? ? v cc + 1.0 0.8 v v diagnostic loopback enable: active- low: input high, v ih input low, v il d loop lv t t l 2.0 0 ? ? v cc + 1.0 0.8 v v parallel output clock 6 : output high, v oh output low, v ol differential voltage swing, ? v diff s-e voltage swing, ? v single pc lk p/n differential lvpecl v cc ? 1.15 v cc ? 1.95 800 400 ? ? ? ? v cc ? 0.6 v cc ? 1.45 1900 950 v v mv mv parameter symbol logic min typ max unit parallel output clock: output high, v oh output low, v ol poc lk p/n differential lvpecl v cc ? 1.3 v cc ? 2.0 ? ? v cc ? 0.7 v cc ? 1.4 v v poc lk duty cycle ? ? 40 ? 60 % output data signal levels 1 : output high, v oh output low, v ol rxq[0:15]p/n differential lvpecl v cc ? 1.3 v cc ? 2.0 ? ? v cc ? 0.7 v cc ? 1.4 v v rxq[0:15] rise/fall time 2 ?? ?? 1.0ns frame pulse: output high, v oh output low, v ol fp lvpecl v cc ? 1.3 v cc ? 2.0 ? ? v cc ? 0.7 v cc ? 1.4 v v loss-of-signal output: output high, v oh output low, v ol los lvttl 2.4 0 ? ? v cc 0.4 v v out-of-frame input: input high, v ih input low, v il oof lvttl 2.0 0.0 ? ? ttl v cc + 1.0 0.8 v v frame enable input input high, v ih input low, v il framen lvttl 2.0 0.0 ? ? ttl v cc + 1.0 0.8 v v
18 18 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 timing characteristics transmitter data input timing the ca16 transponder utilizes a unique fifo to decouple the internal and external (pic lk ) clocks. the fifo can be initialized, which allows the system designer to have an infinite pc lk -to-pic lk delay through this interfacing logic (asic or commercial chip set). the configuration of the fifo is dependent upon the i/o pins, which comprise the synch timing loop. this loop is formed from pherr to phinit and pc lk to pic lk . the fifo can be thought of as a memory stack that can be initialized by phint or lockdet. the pherr signal is a pointer that goes high when a potential tim- ing mismatch is detected between pic lk and the inter- nally generated pc lk clock. when pherr is fed back to phinit, it initializes the fifo so that it does not over- flow or underflow. the internally generated divide-by-16 clock is used to clock-out data from the fifo. phinit and lockdet signals will center the fifo after the third pic lk pulse. this is done to ensure that pic lk is stable. this scheme allows the user to have an infinite pc lk to pic lk delay through the asic. once the fifo is cen- tered, the pc lk and pic lk can have a maximum drift of 5 ns. during normal operation, the incoming data is passed from the pic lk i nput timing domain to the internally generated divide-by-16 pc lk timing domain. although the frequency of pic lk and pc lk is the same, their phase relationship is arbitrary. to prevent errors caused by short setup or hold times between the two domains, the timing generator circuitry monitors the phase rela- tionship between pic lk and pc lk . when an fifo timing violation is dete cted, the phase error (pherr) s ignal pulses hi gh. if the condition per- sists, pherr will remain high. when pherr is fed back into the phinit input (by shorting them on the printed-circuit board [pcb]), phinit will initialize the fifo if phinit is held high for at least two byte clocks. the initialization of the fifo prevents pc lk and pic lk from concurrently trying to read and write over the same fifo bank. during realignment, one-to-three bytes (16 bits wide) will be lost. alternatively, the customer logic can take in the pherr signal, process it, and send an output to the phinit input in such a way that only idle bytes are lost during the initialization of the fifo. once the fifo has been initialized, pherr will go inactive.
19 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer timing characteristics (continued) input timing mode 1 in the configuration shown in figure 5, pherr to phinit has a zero delay (shorted on the pcb) and the pc lk is used to clock 16-bit-wide data out of the cus- tomer asic. the fifo in the multiplexer ia 16-bits wide and six registers deep. the pc lk and pic lk signals respectively control the read and write counters for the fifo. the data bank from the fifo has to be read by the internally generated clock (pc lk ) only once after it has b een writ- ten by the pic lk input. since the delay in the customer asic is unknown, the two clocks (pc lk and pic lk ) might drift in respect to each other and try to perform the read and writer oper- ation on the same bank in the fifo at the same time. however, before such a clock mismatch can occur, pherr goes high and, if externally connected to phinit, will initialize the fifo provided phinit remains high for at least two byte clocks. one to three 16-bit words of data will be lost during the initialization of the fifo. figure 5. block diagram timing mode 1 customer logic ca16 transponder fifo pll divider oscillator t x refclk 16 pherr phinit pclk piclk lockdet 155.52 mhz 20 ppm timing generator internal txd[0:15] clock data centers fifo pclk d q 1-1121(f).b
20 20 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 transmitter data input timing (continued) input timing mode 2 to avoid the loss of data, idle or dummy bytes should be sent on the t x d[0:15] bus whenever pherr goes high. in the configuration shown in figure 6, the pherr signal is used as an input to the customer logic. upon detecting a high on the pherr signal, the customer logic should return a high signal, one t hat remains high for at least two byte-clock cycles, to the phinit input of the ca16. also, when pherr goes high, the customer logic should start sending idle or dummy bytes to the ca16 on the t x d[0:15] bus. this should continue until pherr goes low. the fifo is initialized two-to-eight byte clocks after phinit goes high for two byte clocks. pherr goes low after the fifo is initialized. upon detecting a low on pherr, the customer logic can start sending real data bytes on t x d[0:15]. the two timing loops (pc lk to pic lk and pherr to phinit) do not have to be of equal length. figure 6. block diagram timing mode 2 customer logic ca16 transponder fifo pll divider oscillator t x refclk 16 pherr phinit pclk piclk lockdet 155.52 mhz 20 ppm timing generator internal txd[0:15] clock data centers fifo pclk d q 1121(f).b
21 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer timing characteristics (continued) forward clocking in some applications, it is necessary to forward-clock the data in a sonet/sdh system. in this application, the reference clock from which the high-speed serial clock is synth esized and the parallel data clock both originate from the same source on the customer appli- cation circuit. the timing control logic in the ca16 tran- sponder transmitter automatically generates an internal load signal that has a fixed relationship to the reference clock. the logic takes into account the variation of the reference clock to the internal load signal over temper- ature and voltage. the connections r equired to imple- ment this clocking method are shown in figure 7. the setup and hold times for pic lk to txd[0:15] must be met by the customer logic. possible problems: to meet the jit ter generation specifi- cations required by sonet/sdh, the jitter of the refer- ence clock must be minimized. it could be difficult to meet the sonet jitter generation specifications using a reference clock generated from the customer logic. figure 7. forward clocking of the ca16 transponder customer logic ca16 transponder fifo pll divider t x refclk 16 pherr phinit pclk piclk lockdet timing generator internal txd[0:15] clock data centers fifo pclk oscillator 155.52 mhz 20 ppm t x refclk clock buffer 1-1122(f).a
22 22 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 timing characteristics (continued) pc lk -to-pic lk timing after powerup or reset, the lockdet signal will go active, signifying that the pll has locked to the clock provided on the t x r ef c lk input. the fifo is initialized on the third pic lk after lockdet goes active. the pc lk -to-pic lk delay (t d ) can have any value before the fifo is initialized. the t d is fixed at the third piclk after lockdet goes active. once the fifo is initial- ized, pc lk and pic lk cannot drift more than 5.2 ns; tch cannot be more than 5.2 ns. figure 8. pc lk -to-pic lk timing pclk piclk lockdet active 3rd is initalized at the third rising edge of piclk after lockdet goes active. pclk-to-piclk delay is fixed and fifo 2nd 1st tch tch td td 1-1123(f)
23 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer timing characteristics (continued) pherr/phinit case 1?pherr and phinit are shorted on the printed-circuit board: phinit would go high whenever there is a potential tim- ing mismatch between pc lk and pic lk . phinit would remain high as long as the timing mismatch between pc lk and pic lk . if phinit is high for more t han two byte clocks, the fifo will be initialized. phinit w ill ini- tialize the fifo two-to-eight byte clocks after it is high for at least two byte clocks, pherr (and thus phinit) goes active once the fifi is initialized. case 2?pherr signal is input to the customer logic and the customer logic outputs a signal to phinit: another possible configuration is where the pherr signal is input into the customer logic and the customer logic sends an output to the phinit input. however, the customer logic must ensure that, upon detecting a high on pherr, the phinit signal remains high for more than two byte clocks. if phinit is high for less than two byte clocks, the fifo is not guaranteed to be initialized. also, the customer logic must ensure that phinit goes low after the fifo is initialized (pherr goes low). figure 9. pherr/phinit timing pherr phinit pclk piclk internal pclk minimum pulse width required to center the fifo 2 byte clocks 2?8 byte clocks customer asic sends a minimum pulse width of 2 byte clocks upon detecting a high on pherr fifo is initialized 2?8 byte clocks after phinit is high for 2 byte clocks pherr goes high on detecting a fifo timing error 1125(f)
24 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 timing characteristics (continued) t ransmitter data input timing (continued) figure 10. ac input timing 1. 20% to 80%; 330 ? to gnd. figure 11. receiver output timing diagram table 9. transmitter ac timing characteristics symbol description min max unit t st x d txd[0:15] setup time w. r. t. pic lk 1.5 ? ns t ht x d txd[0:15] hold time w. r. t. pic lk 0.5 ? ns ?pc lk p/n duty cycle 40 55 % ?pic lk p/n duty cycle 40 60 % t ppic lk pic lk -to-pic lk drift after fifo centered ? 5 ns table 10. receiver ac timing characteristics symbol description min max unit ?poc lk duty cycle 45 55 % ? rxd[15:0] rise and fall time 1 ?1.0ns tp pout poc lk low to rxd[15:0] valid propagation delay ?1 1 ns ts pout rxd[15:0] and fp setup time w. r. t. poc lk 2?ns th pout rxd[15:0] and fp hold time w. r. t. poc lk 2?ns piclkp txd[0:15] t stxd t htxd poclkp fp tp pout ts pout th pout rxd[15:0]
25 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer figure 12. frame and byte detection 1-1024(f) figure 13. oof timing (framen = high) recovered clock oof serial data rxd[15:0] roclk a1 a1 a1 a2 a2 a2 a2 a2 a2 a1, a1 a1, a1 a1, a1 a2, a2 a2, a2 a2, a2 a2, a2 invalid data valid data fp oof fp search boundary detection enabled timing characteristics (continued) receiver framing note: future versions of the cooled transponder will not support the frame-detect function. figure 12 shows a typical reframe sequence in which a byte realignment is made. the frame and byte bound- ary detection is enabled by the rising edge of oof. both the frame and byte b oundar ies are recognized upon receipt of the first a2 byte following three consec- utive a1 bytes. the third a2 byte is the first data byte to be reported with the correct byte alignment on the out- going data bus (rxd[15:0]). concurrently, the frame pulse (fp) is set high for one poc lk cycle. the frame and byte boundary detection block is acti- vated by the rising edge of oof and stays active until the first fp pulse. figure 13 shows the frame and byte boundary detec- tion activation by a rising edge of oof and deactiva- tion by the first fp pulse. figure 14 shows the frame and byte boundary detec- tion by the activation of a rising edge of oof and deac- tivation by the framen input. 1-1023(f)r.3
26 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 timing characteristics (continued) 1-1025(f) figure 14. framen timing wavelength selection when the wavelength select (ws) pin is at a logic low or open circuited, the optical wavelength from the ca16 transmitter will be a nominal wavelength as determined by the d evice code purchased. if the ws pin is pulled high (logic 1), the optical wavelength will change to the next lower itu channel number (100 ghz spacing, will increase approximately 0.8 nm). during the wavelength change, the transmitter?s optical output will be disabled and the wavelength deviation error alarm will be active until the wavelength has stabilized at its new value. the lsralm will also be active (logic 1) during the wavelength change process. boundary detection enabled oof framen fp search
27 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer qualification and reliability to help ensure high product reliability and customer satisfaction, agere systems inc. is committed to an inten sive quality pro-gram that starts in the design phase and proceeds through the manufacturing process. opt oelect ronics modules are qualified to agere internal standards using mil-std-883 test methods and procedures and using sampling techniques consistent with telcordia technologies * requirements. this qualification program fully meets the intent of telcordia technologies reliability practices tr-nwt-000468 and t a - t sy -000983. in addition, the agere optoelectronics design, development, and manufacturing facility has been certified to be in full compliance with the latest iso ? 9001 quality system standards. * telcordia technologies is a trademark of telcordia technologies, inc. ? iso is a registered trademark of the international organization for standardization. laser safety information class i laser product all versions of the ca16-type transponders are classified as class i laser products per fda/cdrh, 21 cfr 1040 laser safety requirements. the transponders have been registered/certified with the fda under accession number 8720009. all versions are classified as class i laser products per iec ? 825-1:1993. caution: use of controls, adjustments, and procedures other than those specified herein may res ult in hazardous laser radiation exposure. this product complies with 21 cfr 1040.10 and 1040.11. 8.8 m single-mode pigtail with connector. wavelength = 1.5 m. maximum power = 2.0 mw. product is not shipped with power supply. because of size constraints, laser safety labeling is not affixed to the module but is attached to the outside of the shipping carton. notice unterminated optical connectors can emit laser radiation. do not view with optical instruments. electromagnetic emissions and immunity the ca16 transponder will be tested against cenelec e n50 081 part 1 and part 2, fcc 15, class b limits for emissions. the ca16 transponder will be tested against cenelec e n50 082 part 1 immunity r equirements. ? iec is a registered trademark of the international electrotechnical commission.
28 agere systems inc. ca16-type 2.5 gbits/s dwdm transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demultiplexer march 2001 outline diagram dimensions are in inches and (millimeters) (for initial samples; production version will be slightly smaller). 1-1103(f) 4.00 (101.6) 3.50 (88.9) 1.02 (25.91) 0.76 (19.3) 0.25 (6.4) 1.65 (41.9) 0.87 (22.1) 0.55 (14.0) 0.015 (0.38) 0.20 (5.08) 0.29 (7.4) 0.17 (4.3) 0.45 (11.4) 0.30 (7.6) 0.83 (21.1) 1.84 (46.7) 0.83 (21.1) 1.70 (43.2) 1.80 (45.7) (3x) m2.5 x 0.45 mounting holes 2 mm maximum length into package
29 agere systems inc. advance data sheet ca16-type 2.5 gbits/s dwdm transponder with march 2001 16-channel 155 mbits/s multiplexer/demultiplexer ordering information * other connectors may be made available. table 11. ordering information ? for specific order codes for these products, pl ease contact your local agere account manager. related product information code application connector comcode ca16a2caa unspecified wavelength (1800 ps-nm) sc 108701475 ca16a2faa unspecified wavelength (1800 ps-nm) fc/pc 108701483 ca16a2cnn specified wavelength (1800 ps-nm) sc ? ? ca16a2fnn specified wavelength (1800 ps-nm) fc/pc ? ? ca16b2caa unspecified wavelength (3000 ps-nm) sc 108701491 CA16B2FAA unspecified wavelength (3000 ps-nm) fc/pc 108701509 ca16b2cnn specified wavelength (3000 ps-nm) sc ? ? ca16b2fnn specified wavelength (3000 ps-nm) fc/pc ? ? table 12. related product information description document number using the lucent tec hnologies tr ansp onder test b oard application note ap00-017opto order code: 16 xx x xx ca ? ?? basic part number stm level application 16 = stm-16 (sonet oc-48) a2 = 1800 ps-nm (100 km) options connector * c = sc f = fc b2 = 3000 ps-n (170 km) aa = unspecified 17?61 = itu frequency (191.7 thz?196.1 thz)
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liabi lity is assumed as a result of their use or applicat ion. st is a registered trademark of agere systems inc. copyright ? 2001 agere systems inc. all rights reserved printed in u.s.a. march 2001 ds01-120opto (replaces ds99-352lwp) for additional information, cont act your agere systems account mana ger or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3 201 & 3 210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045

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